IF sampling up to 350 MHz SNR: 67.5 dB, fIN up to Nyquist at 105 MSPS SFDR: 83 dBc, fIN = 70 MHz at 105 MSPS SFDR: 72 dBc, fIN = 150 MHz at 105 MSPS 2 V p-p analog input range On-chip clock duty cycle stabilization On-chip reference and track-and-hold SFDR optimization circuit Excellent linearity
DNL: ±0.25 LSB (typical) INL: ±0.5 LSB (typical) 750 MHz full power analog bandwidth Power dissipation: 1.35 W (typical) at 125 MSPS Twos complement or offset binary data format 5.0 V analog supply oper.
📁 Related Datasheet
AD9256 - DIGITAL AMPLIFIER POWER STAGE (Elite Semiconductor)
AD9256H - DIGITAL AMPLIFIER POWER STAGE (Elite Semiconductor)
AD92580 - DIGITAL AMPLIFIER POWER STAGE (Elite Semiconductor)
AD92580C - DIGITAL AMPLIFIER POWER STAGE (Elite Semiconductor)
